Let's make domestic compute truly work together

Role overview

You will work on hardware architecture, board design, validation, and production introduction for AI hardware and supernode products, turning compute, storage, and heterogeneous acceleration capabilities into reliable deliverables.

Responsibilities

1. Track AI supernode technology trends and execute new AI hardware architecture plans across compute, storage, and heterogeneous systems according to the product roadmap.
2. Participate in hardware specification definition and solution evaluation for customized AI hardware and board products; work with JDM partners on schematic and layout design reviews for motherboards, UBBs, and daughter boards, ensuring hardware design quality throughout the development cycle.
3. Participate in motherboard logic and timing design, plus CPLD development and debugging.
4. Follow AI hardware testing, including functional, signal, and reliability testing; track issues and related bugs to ensure high-quality phase gates across the project.
5. Track PCB and PCBA manufacturing for system boards, drive resolution of production issues, and introduce board-level functional testing on the factory side.

Requirements

1. Bachelor's degree or above in computer systems, electronics, communications, networking, or a related field.
2. 5+ years of x86 or ARM server hardware design experience; strong command of schematic design tools; familiarity with low-speed buses such as UART, SPI, and I2C, plus high-speed buses such as DDR5, PCIe, and Ethernet.
3. Familiarity with ultra-high-speed signal integrity design rules and basic layout placement and routing principles.
4. Familiarity with hardware manufacturing, functional testing, aging tests, system BOM configuration management, and production introduction processes.

Role overview

You will be responsible for AI hardware and supernode product line planning and management, including new product kickoff, development, launch promotion, lifecycle management, and driving product competitiveness and business objectives.

Responsibilities

1. Work with R&D to define product planning and technical platform planning.
2. Own product requirements management, including requirement allocation, changes, and resulting updates to specifications, feasibility analysis reports, and overall solution plans.
3. Coordinate across departments during projects, forming and landing product definitions during kickoff and development stages.
4. Produce comprehensive product materials during launch, and plan and confirm product promotion content.
5. Research AI technology, industry, user, and scenario trends to identify new business and product form opportunities.
6. Align product messaging with business and solution teams, join customer visits, and support customer development.

Requirements

1. Bachelor's degree or above in electronic information, computer science, or a related field.
2. 3+ years of server product experience, with experience across a complete product development cycle; domestic compute server hardware development experience is preferred.
3. Strong communication skills with internal and external stakeholders, with the ability to coordinate progress and drive issues to closure.

What we are building

The foundation of large-model inference is far more than putting accelerator cards into servers. We want to organize domestic accelerators with different models and architectures into a schedulable, observable, and self-healing compute system. You will work from the cluster-wide view, helping more compute get used effectively and turning complex failures into systems that do not require manual firefighting.

Responsibilities

1. Design compute resource pools, quotas, and topology-aware scheduling to reduce fragmentation and shorten queueing time.
2. Build and refine the cluster control plane for nodes, tasks, inference services, elasticity, and capacity planning.
3. Turn slow nodes, performance jitter, hardware failures, and network anomalies into discoverable, diagnosable, and recoverable system events.
4. Work deeply across Linux, containers, NUMA, PCIe, storage, and RoCE/RDMA networks to find real bottlenecks in cluster efficiency.
5. Drive cluster-level adaptation for domestic accelerators and new software-hardware stacks, bringing new compute into production with framework and performance teams.

Requirements

1. Solid understanding of operating systems, computer networks, computer architecture, and distributed systems.
2. Fluency in at least one of C/C++, Go, Rust, or Python, with the willingness to write maintainable systems code.
3. Real project experience in resource scheduling, cluster management, cloud infrastructure, high-performance computing, or distributed platforms.
4. A habit of following logs, metrics, traces, system state, and hardware signals to root cause, rather than stopping at "try restarting it".
5. Engineering judgment and collaboration skills across software, networking, and hardware boundaries.

Nice to have

• Experience with domestic accelerator drivers, runtimes, communication libraries, monitoring tools, or large-scale cluster deployment.
• RDMA, RoCE, InfiniBand, eBPF, DPU/P4, or high-performance network optimization.
• Multiple GPU/NPU stacks, HPC clusters, open-source infrastructure projects, or long-maintained personal systems projects.
• Kubernetes scheduling, Device Plugin, Operator/CRD, container runtime, or resource isolation experience.

What we are building

Performance optimization is detective work inside a system. Starting from a slow request, you trace through the model, framework, operators, communication, and hardware to find where time and memory are actually spent. You will use data to break down bottlenecks, then land stable optimizations on domestic accelerators and real production traffic.

Responsibilities

1. Build trustworthy benchmarking, profiling, and regression systems, continuously improving TTFT, TPOT, throughput, memory usage, and per-token cost.
2. Work deeply on Prefill, Decode, Continuous Batching, request scheduling, KV Cache, Prefix Cache, and disaggregated inference.
3. Optimize tensor parallelism, pipeline parallelism, expert parallelism, and multi-node inference so compute, communication, and memory access overlap better.
4. Drive low-precision quantization, speculative decoding, long context, MoE, multimodal inference, and high-performance operator optimization.
5. Work with framework, cluster, and hardware teams to turn performance prototypes into maintainable, regression-tested production improvements.

Requirements

1. Solid understanding of at least one area among computer architecture, parallel computing, operating systems, or numerical computing.
2. Fluency in Python, C++, or another high-performance computing language, with the ability to read and modify model, framework, or operator code.
3. Understanding of Transformer, Attention, MoE, KV Cache, Prefill/Decode, and related core mechanisms.
4. Ability to form performance hypotheses, design controlled experiments, read profiling data, and prove gains with results rather than intuition.
5. Project experience in inference optimization, GPU/NPU programming, deep learning systems, compilers, or high-performance computing.

Nice to have

• Deep study or modification of vLLM, SGLang, TensorRT-LLM, LMDeploy, PyTorch, or other inference frameworks.
• Operator development and real optimization experience with Triton, TileLang, Ascend C, CUDA, or vendor SDKs.
• Experience with quantization, speculative decoding, model compression, long context, or disaggregated inference.
• Familiarity with collective communication, RDMA, compute-communication overlap, or adaptation across domestic and general-purpose accelerators.

What we are building

Models change, hardware changes, and an inference framework needs to absorb those changes cleanly. You will participate in core engine design, turning new models, new optimizations, and domestic accelerator capabilities into clear, reliable, and extensible framework mechanisms instead of layers of temporary patches.

Responsibilities

1. Develop core modules such as the inference engine, request scheduler, model executor, memory management, and KV Cache management.
2. Enable faster onboarding for LLM, VLM, MoE, long-context, and other new model families through model loading, operator mapping, and execution flow improvements.
3. Build single-node multi-card and multi-node distributed inference capabilities, handling model parallelism, communication, synchronization, and fault tolerance.
4. Design extensible hardware backend and operator interfaces, adapting domestic accelerators, runtimes, communication libraries, and compiler toolchains.
5. Improve service APIs, observability, compatibility, tests, and performance regression systems, while contributing reusable capabilities back to open-source ecosystems.

Requirements

1. Solid understanding of data structures and algorithms, operating systems, concurrent programming, computer architecture, and distributed systems.
2. Fluency in C++, Python, Rust, or another systems programming language, with the ability to handle complex infrastructure software.
3. Experience with inference frameworks, deep learning frameworks, compilers/runtimes, distributed computing, or high-performance computing projects.
4. Understanding of PyTorch and mainstream model execution mechanisms, with the ability to debug from model, graph, operator, memory, and communication layers.
5. Care for code quality and long-term evolution, with extra thought for clear abstractions, compatibility, testing, and maintainability.

Nice to have

• Deep understanding of or contributions to vLLM, SGLang, TensorRT-LLM, LMDeploy, PyTorch, or similar frameworks.
• Experience adapting domestic accelerator SDKs, runtimes, compiler backends, operator libraries, or hardware abstraction layers.
• Familiarity with model parallelism, collective communication, KV Cache, dynamic batching, or disaggregated inference systems.
• Open-source contributions to inference frameworks, compilers, runtimes, or other large infrastructure software projects.